
Interfacing the Standard Parallel Port http://www.senet.com.au/~cpeacock
Interfacing the Standard Parallel Port Page 17
Reserved Currently Reserved.
Under Microsoft’s Extended Capabilities Port Protocol and ISA Interface Standard this
mode is Vendor Specified.
FIFO Test Mode While in this mode, any data written to the Test FIFO Register will be placed into
the FIFO and any data read from the Test FIFO register will be read from the
FIFO buffer. The FIFO Full/Empty Status Bits will reflect their true value, thus
FIFO depth, among other things can be determined in this mode.
Configuration Mode In this mode, the two configuration registers, cnfgA & cnfgB become available at
their designated Register Addresses.
If you are in ECP Mode under BIOS, or if your card is jumpered to use ECP then it is a good
idea to initialize the mode of your ECP port to a pre-defined state before use. If you are using SPP,
then set the port to Standard Mode as the first thing you do. Don't assume that the port will already be
in Standard (SPP) mode.
Under some of the modes, the SPP registers may disappear or not work correctly. If you
are using SPP, then set the ECR to Standard Mode. This is one of the most common mistakes that
people make.
Notes
Note
1
Using Interrupts is available in PDF from
http://www.geocities.com/SiliconValley/Bay/8302/interupt.pdf (62kb)
Note
2
Interfacing the Enhanced Parallel Port is available in PDF from
http://www.geocities.com/SiliconValley/Bay/8302/epp.pdf (33kb)
Note
3
Interfacing the Extended Capabilities Port is available in PDF from
http://www.geocities.com/SiliconValley/Bay/8302/ecp.pdf (53kb)
Craig Peacock’s Interfacing the PC
http://www.senet.com.au/~cpeacock
http://www.geocities.com/SiliconValley/Bay/8302/
Copyright February 1998 Craig Peacock.
Any errors, ideas, criticisms or problems, please contact the author at
[email protected]
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